Publications

  • Book Chapters :
  1. Ghassem Jaberipur, “Redundant Number System Based Arithmetic Circuits,” in Arithmetic Circuits for DSP Applications, edited by Pramod Kumar Meher and Thanos Stouraitis, published by IEEE & Wiley, 2017.

 

  • Journals:
  1. Jaberipur, E. Rahman and J. -A. Lee, ” Balanced Modular Addition for the Moduli Set {2^q,2^(q+-1),2^(2q+1)} via Moduli-( 2^q+-(square root of -1)) Adders,” in IEEE Transactions on Computers, doi: 10.1109/TC.2024.3461235.I.
  2. I. Moghaddasi, G. Jaberipur, D. Javaheri and B. -G. Nam, “RNPE: An MSDF and Redundant Number System-based DNN Accelerator Engine,” in IEEE Access, doi: 10.1109/ACCESS.2024.3426625.
  3. S. Moradi Cherati, G. Jaberipur and L. Sousa, “Sparse Matrix-Vector Multiplication Based on Online Arithmetic,” in IEEE Access, vol. 12, pp. 87653-87664, 2024, doi: 10.1109/ACCESS.2024.3416395.
  4. G. Jaberipur, D. Badri and Jeong-A Lee, “A Parallel Prefix Modulo-( ) Adder via Diminished-1 Representation of residues,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 8, pp. 3104-3108, Aug. 2023, doi: 10.1109/TCSII.2023.3256401.
  5. Belghadr, A. and G. Jaberipur, “Efficient Variable-Coefficient RNS-FIR Filters with no Restriction on the Moduli Set,” Signal, image and video processing, SIViP 16, 1443–1454 (Sep., 2022). doi.org/10.1007/s11760-021-02097-9.
  6. Valavi, H, G. Jaberipur, K. Al-Rahman Youssefi, “Impact of different types of input wire on defect-tolerance of QCA majority voter,” The European Physical Journal Plus, (Aug. 27, 2022) 137:977, DOI: 10.1140/epjp/s13360-022-03134-3.
  7. Jaberipur, G. and F. Ghazanfari, “Impact of Radix-10 Redundant Digit Set [-6,9] on Basic Decimal Arithmetic Operations,” IEEE Trans. On VLSI Systems, to appear, DOI: 10.1109/TVLSI.2021.3120065.
  8. Ahmadpour, Z, and G. Jaberipur, “Up to 8k-bit Modular Montgomery Multiplication in Residue Number Systems with Fast 16-bit Residue Channels,” IEEE Transaction on Computer, To appear. DOI: 10.1109/TC.2021.3086071.
  9. Torabi, Z. G. Jaberipur & S. A. Mirnaseri, “RNS Comparison via Shortcut Mixed Radix Conversion: The Case of Three 4-Moduli Sets,” IETE Journal of Research, DOI: 10.1080/03772063.2021.1902865.
  10. Bakhtavari Mamaghani, S., M.H. Moaiyeri, and G. Jaberipur, “Design of an Efficient Fully Nonvolatile and Radiation-Hardened Majority-Based Magnetic Full Adder Using FinFET/MTJ,” Microelectronics Journal, vol. 103, p. 104864, Sep. 2020.
  11. Hosseini, A., G. Jaberipur, “Complex Exponential Functions: A High-Precision Hardware Realization,” Integration, The VLSI Journal, Vol. 73, pp. 18–29, July, 2020.
  12. Valavi, H., and Jaberipur, “Physically Unclonable Functions Based on Small Delay Defects in QCA,” Semiconductor Science and Technology, Vol. 35, No. 3, pp. , March 2020.
  13. Torabi, Z., G. Jaberipur, and A. Belghadr, “Fast Division in the Residue Number System {2^n+1,2^n,2^n–1} Based On Shortcut Mixed Radix Conversion,” Computers and Electrical Engineering, Vol. 83, No. 5, pp., May 2020.
  14. Jaberipur, G., and B. Nadimi, “Balanced  Adders for Moduli Set ,” IEEE Trans. On Circuits and systems I, Vol. 67, No. 4, PP. 1368-1377, April 2020, DOI: 10.1109/TCSI.2019.2959638
  15. Parhami, B., D Abedi, and G Jaberipur, “Majority Logic, Its Applications, and Atomic-Scale Embodiments,” Computers and Electrical Engineering, Vol. 83, No. 5, May 2020.
  16. Jaberipur, G., A. Belghadr, and S. Nejati, “Impact of diminished-1 encoding on residue number systems arithmetic units and converters,” Computers and Electrical Engineering, Vol. 75, pp. 61–76, 2019.
  17. Jaberipur, G., B. Parhami, and D. Abedi, “Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies,” IEEE Trans. On sustainable computing, Vol. 3, No. 4, pp. 262-273, Dec. 2018, DOI: 1109/TSUSC.2018.2811181.
  18. A. Belghadr, and G. Jaberipur, “FIR Filter Realization via Deferred End-Around Carry Modular Addition,” IEEE Trans. On Circuits and systems, Vol. 65, No. 9, pp. 2878-2888, Sep. 2018, DOI:1109/TCSI.2018.2798595.
  19. S. Amanollahi, and G. Jaberipur, “Extended Redundant-Digit Instruction Set for Energy Efficient Processors,” The ACM Transactions on Embedded Computing Systems, Vol. 17, No. 3, Article No. 70, June 2018, DOI: 10.1145/3202664.
  20. S. Amanollahi, and G. Jaberipur, “Fast Energy Efficient Radix-16 Sequential Multiplier,” IEEE Embedded Systems Letters, Vol. 9, Issue 3, pp. 73, 76, June 2017.
  21. D. Abedi, G. Jaberipur, “Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata,” IEEE Trans. On Circuits and systems II, Vol. 65, No. 1, pp. 106-110, January 2018 DOI: 10.1109/TCSII.2017.2703942.
  22. G. Jaberipur, and A. Belghadr, “(5+2logn)ΔG diminished-1 modulo-(2^n+1) unified adder/subtractor with full zero handling,” Computers and Electrical Engineering, Vol. 61, pp. 95–103, 2017.
  23. M. Sangsefidi, D. Abedi, G. Jaberipur, “Radix-8 Full Adder in QCA with Single Clock-Zone Carry Propagation Delay,” Microprocessors and Microsystems, vol. 51, no. 1, pp. 176-184, DOI: 10.1016/j.micpro.2017.04.005
  24. H. Ghassemi and G. Jaberipur, “The Impact of Excess-Modulo Representation of Residues on Modulo-(2^n–5) Parallel Prefix Addition,” The CSI Journal of Computer Science and Engineering, Vol. 13, No. 2, pp. 48-53, 2016.
  25. S. Amanollahi, and G. Jaberipur, “Architecture-Level Design Space Exploration for Radix-16 Sequential Multipliers,” The CSI Journal of Computer Science and Engineering, Vol. 7, No. 2 & 4 (b), pp. 24-30, 2016.
  26. S. Amanollahi, and G. Jaberipur, “Energy Efficient VLSI Realization of Binary64 Division with Redundant Number Systems,” IEEE Trans. On VLSI Systems, 25, No. 3, pp. 954-961, March 2017
  27. Gorgin, S. and G. Jaberipur, “Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication,” IEEE Trans. On VLSI Systems, 25, No. 1, pp. 75-86, 2017.
  28. Torabi Z. and G. Jaberipur “Fast Low Energy RNS Comparators for 4-Moduli Sets  with ,” Integration, the VLSI Journal, Vol. 55, September 2016, Pages 155–161.
  29. Hosseini A. and G. Jaberipur “Decimal Goldschmidt: A Hardware Algorithm for Radix-10 Division,” Computers and Electrical Engineering, Vol. 53, pp. 40-55, 2016.
  30. Dorrigiv M. and G. Jaberipur, “Conditional Speculative Mixed Decimal/Binary Adders via Binary-Coded-Chiliad Encoding,” Computers and Electrical Engineering, Vol. 50, pp. 39–53, 2016.
  31. Hosseini A. and G. Jaberipur “Decimal Square Root: Algorithm and Hardware Implementation,” Circuits, Systems & Signal Processing, DOI: 10.1007/s00034-015-0215-1.
  32. Torabi Z. and G. Jaberipur “VLSI Realization of Low Power/Cost RNS Comparator via Partitioning the Dynamic Range,” IEEE Trans. On VLSI Systems, DOI: 1109/TVLSI.2015.2484618.
  33. Jaberipur, G. and H. Fatemi Langroudi “(4+2 logn)ΔG Parallel Prefix Modulo-(2^n-3) Adder via Double Representation of Residues in [0,2],” IEEE Trans. On Circuits and systems II, Vol. 62, No. 6, pp. 583-587, June 2015.
  34. D. Abedi, and G. Jaberipur “Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone Based Crossover,” IEEE Trans. On Nanotechnology, Vol. 14, No. 3, pp. 119-122, May 2015.
  35. Ahmadifar H., and G. Jaberipur “A New Residue Number System with 5-Moduli Set: {2^2q,2^q±3,2^q±1},” The Computer Journal, doi: 10.1093/comjnl/bxu084.
  36. Gorgin, S. and G. Jaberipur, “Comment on “High Speed Parallel Decimal Multiplication with Redundant Internal Encodings”,”IEEE Trans. on Computers, Vol. 64, No. 1, pp. 293-294, January 2015.
  37. Gorgin, S., G. Jaberipur, and R. Hashemi Asl “Efficient ASIC and FPGA Implementation of Binary-Coded-Decimal Digit- Multipliers,” Springer Circuits, Systems, and Signal Processing, Vol. 33, No. 12, pp 3883-3899, Dec. 2014.
  38. DorriGiv, M. and G. Jaberipur, “Low Area/Power Decimal Addition with Carry-Select Correction and Carry-Select Sum- digits,” Integration, the VLSI Journal, Vol. 47, No. 4, pp. 443–451, 2014.
  39. Jaberipur, G. and H. Ahmadifar, “A ROM-less Reverse RNS Converter for Moduli Set ,” IET Computer & Digital Techniques, Vol. 8, No. 1, pp. 11-22, 2014.
  40. Pishvaie, A., G. Jaberipur, A. Jahanian, “High Performance CMOS (4; 2) Compressors,” Taylor & Francis International Journal of Electronics, doi: 10.1080/00207217.2014.880133.
  41. Pishvaie, A., G. Jaberipur, A. Jahanian, “Redesigned CMOS (4; 2) compressor for fast binary multipliers,” Canadian Journal of Electrical and Computer Engineering, Vol. 36, No. 3, pp. 111-115, 2013.
  42. Jaberipur, G. and M. Dorrigiv, “Ambiguity-resolving Syntax Definition with Asserted Shift Reduce Sets” Scientia Iranica, Vol. 20, No. 6, pp. 1939-1952, 2013.
  43. Jaberipur, G. and B. Parhami, “Efficient Realization of Arithmetic Algorithms with Weighted Collections of Posibits and Negabits,” IET Computers & Digital Techniques, Vol. 6, No. 5, pp. 259-268, 2012. [PDF]
  44. Pishvaie, A., G. Jaberipur, A. Jahanian, “Improved CMOS (4; 2) Compressor Designs for Parallel Multipliers,”  Computers and Electrical Engineering, Vol. 38, pp. 1703-1716, 2012.
  45. Jaberipur, G., H. Alavi, and S. Nejati, “A Modulo 2n+1 Multiplier with Faithful Representation of Residues,” The CSI Journal of Computer Science and Engineering, Vol. 7, No. 2 & 4 (b), pp. 1-7, 2009 (accepted 7,7,2011).
  46. Kaivani, A. and G. Jaberipur, “Decimal CORDIC Rotation based on Selection by Rounding,” The Computer Journal, Vol. 54, No. 11, pp. 1798-1809 Nov. 2011. [PDF]
  47. Kaivani, A., A. Hosseiny, G. Jaberipur, “Improving the Speed of Decimal Division,” IET Computer & Digital Techniques, Vol. 5, No. 5, pp. 393-404, September 2011. [PDF]
  48. Jaberipur, G., “A Generic Modulo  Adder Based on Stored Negabit Representation of Residues,” The CSI Journal of Computer Science and Engineering, Vol. 6, No. 2 & 4 (b), pp. 29-35, 2008 (Accepted 12, 13, 2010).
  49. Gorgin, S., and G. Jaberipur, “Design and Synthesis of High Speed Low Power Signed Digit Adders,” Journal of Iranian Association of Electrical and Electronics Engineering, Vol. 7, No. 2, pp 7-14, Fall & Winter 2010.
  50. Jaberipur, G. and S. Gorgin, “An improved maximally redundant signed digit adder,”  Computers & Electrical Engineering, Vol. 36, No. 3, pp 491-502, May 2010. [PDF]
  51. Jaberipur, G., B. Parhami and S. Gorgin, “Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value,” IEEE Trans. on Computers, Vol. 59,  No. 5, May 2010, pp 694-706. [PDF]
  52. Kaivani, A., G. Jaberipur, “Fully Redundant Decimal Addition and Subtraction Using Stored Unibit Encoding,” Integration, the VLSI Journal, Vol. 43, No. 1, January 2010, pp 34-41. [PDF]
  53. Jaberipur G., Amir Kaivani, “Improving the Speed of Parallel Decimal Multiplication,” IEEE Trans. on Computers, Vol. 58, No. 11, pp 1539-1552, Nov. 2009. [PDF]
  54. Gorgin, S. and G. Jaberipur, “A Fully Redundant Decimal Adder and its Application in Parallel Decimal Multipliers,” The Micro Electronics Journal, Vol. 40, No. 10, pp. 1471-1481, October, 2009. [PDF]
  55. Jaberipur, G. “A One-step modulo 2n+1 Adder Based on Double-lsb Representation of Residues,” The CSI Journal on Computer Science and Engineering, Vol. 4, No. 2&4, 2006. pp 10-16 (published in April 2009). [PDF]
  56. Jaberipur, G. and B. Parhami, “Constant-Time Addition with Hybrid-Redundant Numbers: Theory and Implementations,” Integration, the VLSI Journal, Vol. 41 No. 1, January 2008, PP. 49–64. [PDF]
  57. Jaberipur, G. and A. Kaivani, “Binary-Coded Decimal (BCD) Digit-Multipliers,” IET Computers, and Digital Techniques, Vol.1, No. 4, pp. 377-381, July 2007. [PDF]
  58. Jaberipur, G. and B. Parhami, “Stored-Transfer Representations with Weighted Digit-Set Encodings for Ultrahigh-Speed Arithmetic,” IET Circuits, Devices, and Systems, Vol. 1, No. 1, pp. 102-110, February 2007. [PDF]
  59. Jaberipur, G., B. Parhami, and M. Ghodsi, “An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding,” Journal of VLSI Signal Processing, Vol. 42, No. 2, pp. 149-158, February 2006. (Reprints available on request from the first author). [PDF]
  60. Jaberipur, G., B. Parhami, and M. Ghodsi, “Weighted Two-Valued Digit-Set Encodings: Unifying Efficient Hardware Representation Schemes for Redundant Number Systems,” IEEE Transaction on Circuits and Systems I, Vol. 52, No. 7, pp. 1348-1357, July 2005. [PDF]
  61. Jaberipur, G. and M. Ghodsi, “High Radix Signed Digit Number Systems: Implementation Paradigms,” Scientia Iranica, Volume 10, Number 4, pp. 383-391, October 2003. [PDF]
  62. Jaberipur; G. “پردازش کارا، نیاز اساسی استاندارد کردن رمز تبادل اطلاعات فارسی ”, Gosaresh-Computer, No. 76, page 19, 1986 (English translation of the title: Efficient Processing: A Central Goal in Standardizing the Persian Information Exchange Code)
  63. Jaberipur; G. “یک راه حل ساده برای مرتب کردن اطلاعات فارسی ” Gosaresh-Computer, No. 74, page 3, 1985 (English translation of the title: A Simple Solution for Sorting Persian Data)
  64. Jaberipur; G., “فارسی‌سازی زبان‌های برنامه‌نویسی ” Gosaresh-Computer, No. 68, page 5, 1985 (English translation of the title: Realizing the Persian Version of Programming Languages)

 

  • Conferences:
  1. Najafi, M. K. Fallah, S. Gorgin, G. Jaberipur and J. -A. Lee, “Poster: Integration of Wearable and Affective Computing via Abstraction and Decision Fusion Architecture,” 2024 IEEE 25th International Symposium on a World of Wireless, Mobile and Multimedia Networks (WoWMoM), Perth, Australia, 2024, pp. 301-303, doi: 10.1109/WoWMoM60985.2024.00055.
  2. Najafi, S. Gorgin, M. K. Fallah, G. Jaberipur and J. -A. Lee, “Low-Power BLACK-ICE Detection for Safety Critical Edge Devices on Roads,” 2024 Fifteenth International Conference on Ubiquitous and Future Networks (ICUFN), Budapest, Hungary, 2024, pp. 636-641, doi: 10.1109/ICUFN61752.2024.10625231. Learning;Sharpness and Glossiness},
  3. Ahmadpour, Z, G. Jaberipur and Jeong-A Lee, “Montgomery Modular Multiplication via Single-Base Residue Number Systems,” to appear in Proc. of the 31st IEEE Symposium on Computer Arithmetic, Malaga, Spain June, 10-12 2024.
  4. Jaberipur, G, S. Gorgin, N. Ahamadian, and Jeong-A Lee, “Modulo-( ) Multiplication with Fully Modular Partial Product Generation and Reduction,” to appear in Proc. of the 30nd IEEE Symposium on Computer Arithmetic, Portland, Oregon, USA, 2023.
  5. Jaberipur, G. and S. Moradi, “Modulo-(2^n+3) Parallel Prefix Addition via Diminished-3 Representation of Residues,” to appear in Proc. of the 26th IEEE Symposium on Computer Arithmetic, June, 10-12, 2019, Kyoto, Japan.
  6. Jaberipur, G., B. Parhami, and D. Abedi, “A Formulation of Fast Carry Chains Suitable for Efficient Implementation with Majority Elements,” in Proc. of the 23nd IEEE Symposium on Computer Arithmetic, pp. 8-15, July, 10-13, 2016, Santa Clara, CA, USA. doi: 10.1109/ARITH.2016.14
  7. Abedi, D. and G. Jaberipur, “Coplanar QCA Serial Adder and Multiplier via Clock-Zone Based Crossovers,” in Proc. Of the 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS2015), Tehran, Iran, DOI:1109/CADS.2015.7377791.
  8. Fatemi, H. and G. Jaberipur, “Modulo-( ) Parallel Prefix Addition via Excess-Modulo Encoding of Residues,” in Proc. of the 22nd IEEE Symposium on Computer Arithmetic, pp. 121-128, June, 22-24, 2015, Lyon, France.
  9. Fatemi, H., G. Jaberipur, “Double {0,1,2} representation Modulo-(2^n-3) adders,” in Proc. Of the 21st International Conference on Systems, Signals, and Image Processing, May 12-15, 2014, Duborvnik, Croatia, pp. 119-122.
  10. Ahmadifar, A., and G. Jaberipur, “Improved modulo- multipliers,” in Proc. Of the 17th CSI International Symposium on Computer Architecture and Digital Systems (CADS2013), Tehran, Iran, pp. 31-35.
  11. Emami, S., M. Dorrigiv, and G. Jaberipur, “Radix-10 addition with Radix-1000 encoding of decimal operands,” in Proc. Of the 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS2012), Shiraz, Iran, pp. 3-9, May 2012.
  12. Pishvaie, A., G. Jaberipur, and A. Jahanian, “سه ورودی xor سریع بر پایه دروازه cmos(4:2) طراحی کمپرسور” in Proc. of 17th CSI Computer Conference, Sharif University of Technology, Tehran, Iran, March, 6-8, 2012 (English translation of the title: Design of a Fast (4; 2) Compressor Based on 3-way XOR Gate).
  13. Jaberipur, G., B. Parhami, and S. Nejati, “On Building General Modular Adders from Standard Binary Arithmetic Components,” Proc. 45th Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA, pp. 154-159, 6-9 November 2011.
  14. Gorgin S. and G. Jaberipur, “A Family of Signed Digit Adders,” in Proc. of the 20th IEEE Symposium on Computer Arithmetic, pp. 112-120, July, 25-27, 2011, Tubingen, Germany. [PDF]
  15. Jaberipur, G. and S. Nejati, “Balanced Minimal Latency RNS Addition for Moduli Set {2n − 1, 2n, 2n + 1},” in Proc. Of the 18th  International Conference on Systems, Signals, and Image Processing, PP. 159-165, 16-18, June 2011, Sarajevo, Bosnia and Herzegovina.
  16. Jaberipur, G. and B. Parhami, “Posibits, Negabits, and Their Mixed Use in Efficient Realization of Arithmetic Algorithms”, in Proc. Of the 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS2010), pp. 3-9, Sep. 23-24, 2010.
  17. Jaberipur, G. and H. Alavi, “A Modulo 2^n+1 Multiplier with Double-LSB Encoding of residues”, in Proc. Of the 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS), pp. 147-150, Sep. 23-24, 2010.
  18. Gorgin, S., G. Jaberipur and B. Parhami, “Design and evaluation of decimal array multipliers,” in proc. of the 43rd Asilomar Conference on Signals, Systems and Computers, pp. 1782-1786, Nov. 2009. [PDF]
  19. Jaberipur G. and B. Parhami, “Unified Approach to the Design of Modulo-(2n ± 1) Adders Based on Signed-LSB Representation of Residues,” in Proc. of the 19th IEEE Symposium on Computer Arithmetic, pp. 57-64, Jun. 8-10, 2009, Portland, USA. [PDF]
  20. Gorgin S. and G. Jaberipur, “Fully Redundant Decimal Arithmetic,” in Proc. of the 19th IEEE Symposium on Computer Arithmetic, pp. 145-152, Jun. 8-10, 2009, Portland, USA. [PDF]
  21. Jaberipur G. and  S. Gorgin, “A High Speed Low Power Signed Digit Adder,” in Proc. Of the 16th Iranian Conference on Electrical Engineering, Tarbiat Modares University, Tehran, Iran, May 13-15, 2008. [PDF]
  22. Jaberipur G. and  S. Gorgin,  “A Nonspeculative One-Step Maximally Redundant Signed Digit Adder,”The 13th int,l CSI Computer Conference, Kish island, Persian Gulf, Iran, March, 9-11, 2008. Also printed in Lecture Notes on Computer Science, CSICC 2008, CCIS 6, pp. 235–242, 2008. [PDF]
  23. Sheikhattar H., V. Rahiman, G. Jaberipur and N. Noroozi, “Design and Implementation issues for the MobFish,” The Twelfth International Conference on Distributed Multimedia Systems, Grand Canyon, USA, Aug. 30, Sep. 1, 2006.
  24. Jaberipur, G., B. Parhami and M. Ghodsi, “Weighted Bit-Set Encodings for Redundant Digit Sets: Theory and Applications,” Proc. 36th Asilomar Conf. Signals Systems and Computers, pp. 1629-1633, November 2002. [PDF]
  25. Jaberipur, G., B. Parhami and M. Ghodsi, “A Class of Stored-Transfer Representations for Redundant Number Systems,” Proc. 35th Asilomar Conf. Signals Systems and Computers, Nov. 2001, pp. 1304-1308. [PDF]
  26. M. Ghodsi, G. Jaberipur and R. Khosravi, “SADL: A Systolic Array Description Language,” Proceedings of 4th CSI Computer Conference (CSICC’98), Sharif University of Technology, Jan. 1999. (in Persian)

 

  • Web Documents:
    • (2008) G. Jaberipur and H. Alavi, “Comment on “Fast Parallel Prefix Modulo 2n+1 Adder,” by Costas Efstathiou et al, in IEEE Trans. Computers, Vol. 53, No. 9 pp. 1211-1216, 2004. [PDF]

 

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