Publication

Journal papers

[35] Zohreh Beiki and Ali Jahanian, DENA: A Configurable Micro-architecture and Design Flow for Bio-medical DNA-based Logic Design, Accepted for publication in the IEEE Transactions on Biomedical Circuits and Systems, 2017.

[34] Armin Belghadr and Ali Jahanian, Three-dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area, Systems, Accepted for publication in World Scientific Journal of Circuits, Systems, and Computers (JCSC), 2017 (ISI-41179).

[33] Sedigheh Farhadtooski and Ali Jahanian, Customized Placement Algorithm of Nanoscale DNA Logic Circuits, Accepted for publication in World Scientific Journal of Circuits, Systems, and Computers (JCSC), 2017 (ISI-41178).

[32] Sharareh Zamanzadeh and Ali Jahanian, ASIC Design Protection against Reverse Engineering during the Fabrication Process using Automatic Netlist Obfuscation Design Flow, In ISC International Journal of Information Security (ISeCure), Vol.8, No.2, pp. 87-98, 2016 (ISC-39082).

[31] Sharareh Zamanzadeh and Ali Jahanian, Self Authentication Path Insertion in FPGA-based Design Flow for Tamper-resistant Purpose, In ISC International Journal of Information Security (ISeCure), Vol. 8, No. 1, pp. 53-60, 2016 (ISC-39081).

[30] Sharareh Zamanzadeh and Ali Jahanian, Security Path: an Emerging Design Methodology to Protect the FPGA IPs against Passive/Active Design Tampering, In Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 32, No. 3, pp: 329-343, 2016. (ISI-36672)+.

[29] Maryam Taajobian and Ali Jahanian, Higher Flexibililty of Reconfigurable Digital Micro/Nano Fluidic Biochips using an FPGA-Inspired Architecture, In Scientia Iranica, Vol. 23, No. 3, 2016. (ISI-36671)+.

[28] Sharareh Zamanzadeh and Ali Jahanian, Higher Security of ASIC Fabrication Process Against Reverse Engineering Attack using Automatic Netlist Encryption Methodology, In Elsevier Microprocessors and Microsystems, Vol.42, pp. 1–9, 2016. (ISI-35087)+.

[27] Mehrshad Vosoughi and Ali Jahanian, Security-aware Register Placement to Hinder Malicious Hardware Updating and Improve Trojan Detectability, The ISC International Journal of Information Security (ISeCure), Vol.7, No.2, 2015. (ISC-35088 )+.

[26] S.H. Daryanavard, M. Eshghi and A. Jahanian, Acceleration of Inter-Task Routing for JIT Compilation Reconfigurable Computing Platform Using Customized Processor, In International review on Computers and Software (IRECOS), Vol 10, No 4, 2015 (ISI-41180).

[25] Hassan Daryanavard, Mohammad eshghi, and Ali Jahanian, A Fast Placement Algorithm for Embedded Just-In-Time Reconfigurable Extensible Processing Platform, Journal of Supercomputing, Vol. 171, pp: 121-143, 2015 (ISI-32383)+.

[24] Marzieh Morsehdzadeh and Ali Jahanian, Three-dimensional Switchbox Multiplexing in Emerging 3D-FPGAs to Reduce Chip Footprint and Improve TSV Usage, Accepted in Elsevier Integration the VLSI Journal, Vol. 50, pp: 81-90, 2015. (ISI-30485)+.

[23] Mahmoud Bakhsizadeh and Ali Jahanian, Trojan Vulnerability Map: an Efficient Metric for Modeling and Improvement of Hardware Security Level , In IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No.11, 2014. (ISI-28456)+.

[22] Ali Mohammad Zarei, Ali Jahanian, RF Resource Planning in Application Specific Integrated Circuits to Improve Timing Closure, In CSI Journal on Computer Science and Engineering, 2014, (SR-28369)+.

[21] Ali Pishvaie, Ghasem Jaberipur and Ali Jahanian, High-performance CMOS (4:2) compressors, In Taylor & Francis International Journal of Electronics, Vol.101, No.11, 2014, (ISI-23618)+.

[20] Zohreh Mohammadi-Arfa and Ali Jahanian, Improved Delay and Process Variation Tolerance of Clock Tree Network in Ultra-large Circuits using Hybrid RF/Metal Clock Routing, In World Scientific Journal of Circuits, Systems, and Computers (JCSC), Vol.23, No.4, 2014. (ISI-24125)+.

[19] Armin Belghadr and Ali Jahanian, Metro-on-FPGA: a feasible solution to improve the congestion and routing resource management in future FPGAs, In Elsevier Integration the VLSI Journal, Vol. 47, No.1, 2014. (ISI-28370)+.

[18] Ali Pishvaie, G. Jaberipur, and Ali Jahanian, Redesigned CMOS (4; 2) compressor for fast binary multipliers, In Canadian Journal of Electrical and Computer Engineering, 2013, Vol.36, No.3, 2013. (ISI-20749)+.

[17] Reza Abdollahi and Ali Jahanian, Improved Timing Closure by Analytical Buffer and TSV Planning in Three-dimensional Chips, In Institute of Electrical, Information and Communication Engineers Transaction on Electronics, Vol. 9, No.24, 2012, (ISI-21114)+.

[16] Yahya Zare and Ali Jahanian, Improved Line Tracking System for Autonomous Navigation of High-Speed Vehicle, In International Journal of Robotics and Automation, Vol. 1, No.3, pp. 31-41, 2012, (SR-21115)+.

[15] A. Pishvaei, Ghasem Jaberipur, and Ali Jahanian, Improved CMOS (4;2) compressor designs for parallel multipliers, In Elsevier Computers & Electrical Engineering, Vol. 12, No. 6, 2012. (ISI-18532)+.

[14] Mohammad Taghi Teimoori, , Ali Jahanian, and Adel Dokhanchi, Performance Improvement and Congestion Reduction of Large FPGAs using On-chip Microwave Interconnects, In Institute of Electrical, Information and Communication Engineers Transaction on Electronics, , Vol. E95-c, No. 10, 2012. (ISI-18122)+.

[13] Arash Farkish and Ali Jahanian, Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation, In Institute of Electrical, Information and Communication Engineers Electronic Express Journal, Vol. 8, No. 24, 2012. (ISI-18110)+.

[12] Mohammad Hossein Moaiyeri, Ali Jahanian, and K. Navi, Comparative Performance Evaluation of Large FPGAs with CNFET- and CMOS-based Switches in Nanoscale, In Nano-micro letters, ISSN: 2150-5551, Vol.3, No.3, 2011. (ISI-16476)+.

[11] Ali Jahanian, Morteza Saheb Zamani and Hamid Safizadeh, Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology, In Elsevier Integration the VLSI Journal, Vol.44, No.2, 2011. (ISI-12993)+.

[10] Ali Jahanian and Morteza Saheb Zamani, Using the chip master planning in automatic ASIC design flow to improve performance and buffer resource management, In Qazvin Islamic Azad University Journal of Computer and Robotics (QJCR), 2011, (SR-23820)+.

[9] Ali Jahanian and Morteza Saheb Zamani, Early buffer planning with congestion control using buffer requirement map, In World Scientific Journal of Circuits, Systems, and Computers (JCSC), Vol. 19, No. 5, pp. 949 973, 2010. (ISI-11105)

[8] Ali Jahanian, Morteza Saheb Zamani, Higher routability and reduced crosstalk noise by asynchronous multiplexing of on-chip interconnects, Transactions on Computer Science and Engineering, In Scientia Iranica International Journal of Science and Technology, Vol. 17, No. 1, pp. 11-24, 2010. (ISI-11086)+.

[7] Mercedeh Sanjabi, Somayeh Maabi, Ali Jahanian, and Sirvan Khalighi, A landmark-based navigation system for high speed cars in the roads with branches, In International Journal of Information Acquisition (IJIA), World Scientific Publishing, Vol.6, No.3, pp. 193-209, 2009, (SR-11104)+.

[6] Ali Jahanian, Morteza Saheb Zamani, and E. Khorram, An Improved Standard Cell Placement Methodology using Hybrid Analytic and Heuristic Techniques, In Qazvin Islamic Azad University Journal of Computer and Robotics (QJCR), Vol.1, No.5, 2008, (SR-11599).

[5] Ali Jahanian and Morteza Saheb Zamani, M. Rezvani, and M. Najibi, Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability, In Springer’s Communications in Computer and Information Science, Advances in Computer Science and Engineering, Germany, pp. 689-696, 2008, (SR-11087)+.

[4] Ali Jahanian and Morteza Saheb Zamani, Using metro-on-chip in physical design flow for congestion and routability improvement, Microelectronics Journal of Elsevier, Vol.39, No. 2, pp.261-274, 2008. (ISI-11082)+

[3] Ali Jahanian and Morteza Saheb Zamani, Buffer distribution in floorplanning stage to decrease the buffer number and congestion control, In The CSI Journal on Computer Science and Engineering, Vol. 5, No. 3, pp. 12-22, 2007, (SR-11085).

[2] Mehdi Saeedi, Morteza Saheb Zamani and Ali Jahanian, Evaluation, prediction and reduction of routing congestion, In Microelectronics Journal of Elsevier, Vol. 38, No. 8, pp. 942-958, 2007. (ISI-11083)+

[1] Ali Jahanian and Morteza Saheb Zamani, Metro-on-Chip: an efficient physical design technique for congestion reduction, In Institute of Electrical, Information and Communication Engineers Electronic Express Journal, Vol.4, No.16, pp.510–516,  2007. (ISI-11084)+

 

Conference papers

[69] Hamed Hossein talaee and Ali Jahanian, Layout Vulnerability Reduction against Trojan Insertion using Security-aware White Space Distribution, In International Symposium on VLSI (ISVLSI), 2017.

[68] Sedigheh Farhadtoosky and Ali Jahanian, A new Cell Placement Algorithm for Localized DNA Logic Circuits Mounted on Origami Surface, In International Conference on DNA Computing and Molecular Programming (DNA22), 2016.

[67] Sharareh Zamanzadeh, Shahram Shahabi and Ali Jahanian, Using the netlist scrambling in ASIC design flow to improve security against reverse engineering, Security Improvement of FPGA Configuration File Against the Reverse Engineering Attack, 2016.

[66] Vahid Boreiri and Ali Jahanian, An Scale-able Design methodology for multi-stage DNA circuits, In International Conference on New Research Achievements in Electrical & Computer Engineering (CBCONF), 2016.

[65] Payman Talebian and Ali Jahanian, Isolating the Register-bank Trojans in General-purpose Microprocessors using Secure Programming, In International Conference on New Research Achievements in Electrical & Computer Engineering (CBCONF), 2016.

[64] Atefe Taheri, Ali Jahanian and Behin Molaie, Parallelizing the Coarsening Phase of Hyper-Edge Partitioning on the GPU Platform, In International Conference on Advanced Computer Theory and Engineering, 2016.

[63] Sedigheh Farhadtooski and Ali Jahanian, A new Design flow for DNA-based integrated circuit design as an emerging VLSI Technology, In International Conference on Applied Research in Computer Engineering and Information technology, 2015.

[62] Alireza Abdoli and Ali Jahanian, Fault-tolerant architecture and CAD algorithm for field-programmable pin-constrained digital microfluidic biochips, In The CSI Symposium on Real-Time and Embedded Systems and Technologies (RTEST), 2015.

[61] Sharareh Zamanzadeh and Ali Jahaian, Using the netlist scrambling in ASIC design flow to improve security against reverse engineering, International Conference on Information Security and Cryptography, 2015, (41542).

[60] Bahareh Ahmadi Haji, Mehrshad Vosoughi, and Ali Jahanian, Improved security of SRAM modules against power attack through output transition Equalization, In International Conference on Information Security and Cryptography, 2015, (41541).

[59] Zohreh Beiki and Ali Jahanian, DENA: a Configurable Architecture for Multi-stage DNA Logic Circuit Design, In 21th International Conference on DNA Computing and Molecular Programming (DNA21), 2015, (????).

[58] Ali Abdoli and Ali Jahanian, A General-Purpose Field-Programmable Pin-Constrained Digital Microfluidic Biochip, In CSI International Symposium on Computer Architecture and Digital Systems (CADS), 2015, (36674).

[57] Hassan Daryanavard, Aida Parvizian, Ali Jahanian, and Mohammad Eshghi, Design of CAD ASIP for JIT extensible processor: case study on simulated annealing placer , In 23th Iranian Conference on Electrical Engineering (ICEE), 2014, (28334).

[56] Shahram Shahabi and Ali Jahanian, Improved Switchbox Structure against Reverse Engineering of FPGA Bitstream, In 23th Iranian Conference on Electrical Engineering (ICEE), 2015, (32384).

[55] Omid Abdi and Ali Jahanian, A New Nano-scale Differential Logic Style for Power Analysis Attack, In 23th Iranian Conference on Electrical Engineering (ICEE), 2015, (32385).

[54] Hassan Daryanavard, A. Parvizian, Ali Jahanian, and Mohammad Eshghi, Design of CAD ASIP for JIT extensible processor: case study on Simulated Annealing placer, In 22th Iranian Conference on Electrical Engineering (ICEE), 2014, (28334).

[53] Atefeh Taheri and Ali Jahanian, Parallelizing the hyper-edge coarsening algorithm on GPU architecture, In 22th Iranian Conference on Electrical Engineering (ICEE), 2014, (28333).

[52] Abbas Haddad, M. Taajobian, and Ali Jahanian, A new programmable architecture for microfluidic biochips, In 22th Iranian Conference on Electrical Engineering (ICEE), 2014, (28331).

[51] M. Jerengi, Ali Jahanian, and M.H. Moayeri, A new cell library for Carbon nano-tube tecgnology, In International CSI Computer Conference, 2014 (27682).

[50] Ali Mohammad Zarei and Ali Jahanian, RF resource planning in application specific integrated circuits to improve timing closure, In CSI International Symposium on Computer Architecture and Digital Systems (CADS), 2013, (25101).

[49] Adel Hosseiny, Saba Amanollahi, R. Hashemi and Ali Jahanian, Improved performance and resource usage of FPGA using resource-aware design: the case of decimal array multiplier, In CSI International Symposium on Computer Architecture and Digital Systems (CADS), 2013, (25102).

[48] Sharareh Zamanzadeh and Ali Jahanian, Improved hardware security in ASIC design flow using wire scrambling methodology, In International Conference on Very Large Scale Integration (VLSI-SoC), Turkey, 2013, (28330).

[47 Ali Mohammad Zarei and Ali Jahanian, Performance improvement of ASICs using RF interconnect planning, In International CSI Computer Conference, 2013, (22127).

[46] Mehrshad Vosoughi and Ali Jahanian, Hardware Trojan avoidance using a new clock tree construction algorithm, In International CSI Computer Conference, 2013, (22128).

[45] Zohreh Mohammadi Arfa and Ali Jahanian, Clock tree network using hybrid RF/metal clock routing , In Sharif Conference on Future Electronics, 2013, (21205).

[44] Nazanin Ghasemian and Ali Jahanian, A new nanowire-based FPGA to improve routing congestion and routability, In Sharif Conference on Future Electronics, 2013, (21206).

[43] Bahareh Pourshirazi and Ali Jahanian, RF-Interconnect resource assignment and placement algorithms in application specific ICs to improve performance and reduce routing congestion, In EuroMicro Digital System Design (DSD), 2012, (19464).

[42] Samaneh Talebi and Niloofar Abolghasemi, and Ali Jahanian, EJOP: an extensible Java processor with reasonable performance/flexibility trade-off, In EuroMicro Digital System Design (DSD), 2012, (21116).

[41] S. Amanollahi and Ali Jahanian, Edu3D: a simple and efficient platform for education of three-dimensional physical design automation algorithms, In Design, Automation and Test in Europe University booth (DATE), 2012, (20750).

[40] Marzieh Morshedzadeh and Ali Jahanian, Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage, In Great Lakes Symposium on VLSI (GLSVLSI), 2012, (21198).

[39] Mona Nasehi, Ali Jahanian, and H. R. Zarandi, Modeling, evaluation and mitigation of SEU error in three-dimensional FPGAs, In CSI International Symposium on Computer Architecture and Digital Systems (CADS), 2012, (21202).

[38] Fatima Khoonbani and Ali Jahanian, Improved performance and power consumption of three-dimensional FPGAs using Carbon Nanotube interconnects, In International Symposium on Computer Architecture and Digital Systems (CADS), 2012, (21203).

[37] Mercedeh Sanjabi, N. Miralaei, S. Amanollahi, and Ali Jahanian, ParSA: parallel simulated annealing placement algorithm for multi-core systems, In International Symposium on Computer Architecture and Digital Systems (CADS), 2012, (21204).

[36] Ali Marashi and Ali Jahanian, TrueFlex: a flexible and efficient evaluation platform for networked automotive systems, In 20th Iranian Conference on Electrical Engineering (ICEE), 2012, (21117).

[35] Niloofar Abolghasemi, Samaneh Talebi, and Ali Jahanian, Architecture and custom instructions for customizing the Java processor to improve execution performance, In 20th Iranian Conference on Electrical Engineering (ICEE), 2012, (18534).
[34] A. Pishvaei, G. Jaberipur, and Ali Jahanian, ‘Redesigned CMOS (4; 2) compressor for fast binary multipliers, In 20th Iranian Conference on Electrical Engineering (ICEE), 2012, (18531).

[33] Amin Malekpour, S. Malekpour, and Ali Jahanian, ‘Design, implementation and improvement of decimal parallel multiplier on ASIC and FPGA, In 20th Iranian Conference on Electrical Engineering (ICEE), 2012, (18530).

[32] A. Pishvaei, Ghasem Jaberipur, and Ali Jahanian, High-speed 4:2 compressor design based on 3-input XOR gate, In 17th CSI Computer Conference, 2012, (20380).

[31] Somayyeh Maabi, Mercedeh Sanjabi, Ali. Jahanian, S. Khalighi, Landmark-based car navigation with overtake Capability in multi-agent environments, In International Conference on Agents and Artificial Intelligence, 2012, (20751).

[30] Behzad Salami, Ali Jahanian, and Morteza Saheb Zamani, VMAP: a Variation Map-aware Placement Algorithm for Leakage Power Reduction in FPGAs, In EuroMicro Digital System Design (DSD), Finland, 2011, (20752).

[29] Mojgan Malekshahi Rad and Ali Jahanian, A CNT/Metal Hybrid Routing Architecture to Improve Performance of Ultra-Large FPGAs, In International Conference on Computer Design and Engineering (ICCDE), 2011, (21201).

[28] Saba Amanollahi and Ali Jahanian, EduCAD: an Efficient, Flexible and Easily Revisable Physical Design Tool for Educational Purposes, In Design, Automation and Test in Europe University booth (DATE), 2011, (21118).

[27] Adel Dokhanchi,Ali Jahanian, E. Mehrshahi, and M. Taghi Teimoori, Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage, In International Symposium on VLSI (ISVLSI), 2011, (20669).

[26] Zohreh Mohammadi-Arfa, Ali Jahanian, A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion, In International Symposium on VLSI (ISVLSI), 2011, (?????).

[25] Mehdi Alipour, M. Seyed Javadi, and Ali Jahanian, Congestion and Track Usage Improvement of Large FPGAs Using Metro-on-FPGA Methodology, In Great Lakes Symposium on VLSI (GLSVLSI), 2011, (21199).

[24] Z. Mohammadi-Arfa, Ali Jahanian, Using On-chip RF-Interconnects to Optimize Clock Distribution Network, In 19th Iranian Conference on Electrical Engineering (ICEE), 2011, (18124).

[23] A. Farkish and Ali Jahanian, Parallelizing the PathFinder Global Routing Algorithm using Multi-core Systems, In 19th Iranian Conference on Electrical Engineering (ICEE), 2011, (18123).

[22] Ali Jahanian and Morteza Saheb Zamani, “Chip master planning: an efficient methodology to improve design closure and complexity management of ultra large chips, In CSI International Symposium on Computer Architecture and Digital Systems, Iran, 2010, (12041).

[21] Mercedeh Sanjabi, Somayeh Maabi, Ali Jahanian, and Sirvan KhA.ghi, A Light-weight Car Navigation Algorithm for High Speed Agents using Wireless Landmarks, In IEEE International Conference on Information and Automation (ICIA), 2009, (11601).

[20] Mehdi Nabiyouni, Ali Jahanian, Ahmad Razavi, and Morteza Saheb Zamani, A thermal-aware delay model for pass transistor in FPGA switch boxes, In 14th Annual Computer Society of Iran Computer Conference, 2009, (12020).

[19] Ali Jahanian and Morteza Saheb Zamani, Improved performance and yield with Chip Master planning design methodology, In Great Lakes Symposium on VLSI (GLSVLSI), pp.185-190, 2009, (12200).

[18] Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian, Morteza Saheb Zamani, Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network , In Design and Automation Conference in Europe (DATE), pp.833,838, 2009, (11606).

[17] Ali Jahanian and Morteza Saheb Zamani, Performance and timing yield enhancement using Highway-on-Chip Planning, In EuroMicro Digital System Design, Italy, 2008, (12042).

[16] Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, and Morteza Saheb Zamani, Performance improvement of physical retiming with shortcut insertion, In International Symposium on VLSI (ISVLSI), pp.215-220, 2008, (11121).

[15] Ali Jahanian and Morteza Saheb Zamani, Using asynchronous serial transmission in physical design for congestion reduction, In IEEE East-West Design and Test Conference, pp. 390-395, 2007, (12045).

[14] Ali Jahanian and Morteza Saheb Zamani, Buffer planning using the buffer requirement map with congestion control, In 13th Annual Computer Society of Iran Computer Conference, 2008, (12021).

[13] Ali Jahanian and Morteza Saheb Zamani, Improved timing closure by early buffer planning in floor-placement design flow, In IEEE/ACM Great Lakes Symposium on VLSI, pp. 558-563, 2007, (12019).

[12] Ali Jahanian and Morteza Saheb Zamani, Multi-level buffer block planning and buffer insertion for large design circuits, In International Symposium on VLSI (ISVLSI), pp. 411-415, 2006, (11123).

[11] Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian, “Prediction and reduction of routing congestion”, In ACM International Symposium on Physical Design (ISPD), pp. 72-77, 2006, (12046).

[10] Ali Jahanian and Morteza Saheb Zamani, Buffer insertion during placement with floorplanning information, In 12th Annual Computer Society of Iran Computer Conference, 2006, (12022).

[9] Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian, Congestion prediction: from metric definition to routing estimation, In IEEE International Conference on Microelectronics, pp. 183-188, 2005, (12047).

[8] Mehdi Saeedi, Morteza Saheb Zamani, and Ali Jahanian, An efficient congestion reduction algorithm based on contour plotting, In International Conference on Microelectronics, pp. 942-958, 2005, (12048).

[7] Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian, and Neda Zolfaghari, Efficient host-independent coprocessor architecture for speech coding algorithms, In ACM EuroMicro Symposium on Digital system Design, pp. 227-230, 2005, (12043).

[6] Mohammad Kazem Akbari, Ali Jahanian, Mohsen Naderi, and Bahman Javadi, Area efficient, low power and robust design for add-compare-select units, In ACM EuroMicro Digital System Design, pp. 611-614, 2004, (12044).

[5] Hamid Noori, Hamid Safizadeh, Mehdi Sedighi, and Ali Jahanian, Empowering RISC processors for speech coding algorithms using a portable coprocessor architecture, In Electronic Design Processes Workshop, Monterey, USA, April 2004, (?????).

[4] Ali Jahanian and Mohammad Reza Razzazi, Feasibility of using component based software formal verification by hardware formal verification tools, In 10th Annual Computer Society of Iran Computer Conference, 2004, (12026).

[3] Ali Jahanian, Morteza Saheb Zamani, and Esmaile Khorram, A hybrid heuristically and mathematically approach for VLSI standard cell placement, In 10th Annual Computer Society of Iran Computer Conference, 2004, (12025).

[2] Mojtaba Tashakkori, Payman Adibi, Ali Jahanian, and A. Nourollah, Ant colony solution dynamic Steiner tree problem, In Proceedings of 8th Annual Computer Society of Iran Computer Conference, pp: 465-471, 2003, (12024).

[1] Hossein Pedram and Ali Jahanian, Hardware-Software Co-Simulation, In Proceedings of 2th Annual Computer Society of Iran Computer Conference, 1998, (12023).