Journal Papers

[35] Zohreh Beiki and Ali Jahanian, DENA: A Configurable Micro-architecture and Design Flow for Bio-medical DNA-based Logic Design, In IEEE Transactions on Biomedical Circuits and Systems, DOI: 10.1109/TBCAS.2017.2708747, PP.1-10, 2017 (ISI-41909).

[34] Armin Belghadr and Ali Jahanian, Three-dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area, In World Scientific Journal of Circuits, Systems, and Computers (JCSC), Vol.26, No.10, 2017 (ISI-41179).

[33] Sedigheh Farhadtooski and Ali Jahanian, Customized Placement Algorithm of Nanoscale DNA Logic Circuits, In World Scientific Journal of Circuits, Systems, and Computers (JCSC), , Vol.26, No.10, 2017 (ISI-41178).

[32] Sharareh Zamanzadeh and Ali Jahanian, ASIC Design Protection against Reverse Engineering during the Fabrication Process using Automatic Netlist Obfuscation Design Flow, In ISC International Journal of Information Security (ISeCure), Vol.8, No.2, pp. 87-98, 2016 (ISC-39082).

[31] Sharareh Zamanzadeh and Ali Jahanian, Self Authentication Path Insertion in FPGA-based Design Flow for Tamper-resistant Purpose, In ISC International Journal of Information Security (ISeCure), Vol. 8, No. 1, pp. 53-60, 2016 (ISC-39081).

[30] Sharareh Zamanzadeh and Ali Jahanian, Security Path: an Emerging Design Methodology to Protect the FPGA IPs against Passive/Active Design Tampering, In Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 32, No. 3, pp: 329-343, 2016. (ISI-36672)+.

[29] Maryam Taajobian and Ali Jahanian, Higher Flexibililty of Reconfigurable Digital Micro/Nano Fluidic Biochips using an FPGA-Inspired Architecture, In Scientia Iranica, Vol. 23, No. 3, 2016. (ISI-36671)+.

[28] Sharareh Zamanzadeh and Ali Jahanian, Higher Security of ASIC Fabrication Process Against Reverse Engineering Attack using Automatic Netlist Encryption Methodology, In Elsevier Microprocessors and Microsystems, Vol.42, pp. 1–9, 2016. (ISI-35087)+.

[27] Mehrshad Vosoughi and Ali Jahanian, Security-aware Register Placement to Hinder Malicious Hardware Updating and Improve Trojan Detectability, The ISC International Journal of Information Security (ISeCure), Vol.7, No.2, 2015. (ISC-35088 )+.

[26] S.H. Daryanavard, M. Eshghi and A. Jahanian, Acceleration of Inter-Task Routing for JIT Compilation Reconfigurable Computing Platform Using Customized Processor, In International review on Computers and Software (IRECOS), Vol 10, No 4, 2015 (ISI-41180).

[25] Hassan Daryanavard, Mohammad eshghi, and Ali Jahanian, A Fast Placement Algorithm for Embedded Just-In-Time Reconfigurable Extensible Processing Platform, Journal of Supercomputing, Vol. 171, pp: 121-143, 2015 (ISI-32383)+.

[24] Marzieh Morsehdzadeh and Ali Jahanian, Three-dimensional Switchbox Multiplexing in Emerging 3D-FPGAs to Reduce Chip Footprint and Improve TSV Usage, Accepted in Elsevier Integration the VLSI Journal, Vol. 50, pp: 81-90, 2015. (ISI-30485)+.

[23] Mahmoud Bakhsizadeh and Ali Jahanian, Trojan Vulnerability Map: an Efficient Metric for Modeling and Improvement of Hardware Security Level , In IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No.11, 2014. (ISI-28456)+.

[22] Ali Mohammad Zarei, Ali Jahanian, RF Resource Planning in Application Specific Integrated Circuits to Improve Timing Closure, In CSI Journal on Computer Science and Engineering, 2014, (SR-28369)+.

[21] Ali Pishvaie, Ghasem Jaberipur and Ali Jahanian, High-performance CMOS (4:2) compressors, In Taylor & Francis International Journal of Electronics, Vol.101, No.11, 2014, (ISI-23618)+.

[20] Zohreh Mohammadi-Arfa and Ali Jahanian, Improved Delay and Process Variation Tolerance of Clock Tree Network in Ultra-large Circuits using Hybrid RF/Metal Clock Routing, In World Scientific Journal of Circuits, Systems, and Computers (JCSC), Vol.23, No.4, 2014. (ISI-24125)+.

[19] Armin Belghadr and Ali Jahanian, Metro-on-FPGA: a feasible solution to improve the congestion and routing resource management in future FPGAs, In Elsevier Integration the VLSI Journal, Vol. 47, No.1, 2014. (ISI-28370)+.

[18] Ali Pishvaie, G. Jaberipur, and Ali Jahanian, Redesigned CMOS (4; 2) compressor for fast binary multipliers, In Canadian Journal of Electrical and Computer Engineering, 2013, Vol.36, No.3, 2013. (ISI-20749)+.

[17] Reza Abdollahi and Ali Jahanian, Improved Timing Closure by Analytical Buffer and TSV Planning in Three-dimensional Chips, In Institute of Electrical, Information and Communication Engineers Transaction on Electronics, Vol. 9, No.24, 2012, (ISI-21114)+.

[16] Yahya Zare and Ali Jahanian, Improved Line Tracking System for Autonomous Navigation of High-Speed Vehicle, In International Journal of Robotics and Automation, Vol. 1, No.3, pp. 31-41, 2012, (SR-21115)+.

[15] A. Pishvaei, Ghasem Jaberipur, and Ali Jahanian, Improved CMOS (4;2) compressor designs for parallel multipliers, In Elsevier Computers & Electrical Engineering, Vol. 12, No. 6, 2012. (ISI-18532)+.

[14] Mohammad Taghi Teimoori, , Ali Jahanian, and Adel Dokhanchi, Performance Improvement and Congestion Reduction of Large FPGAs using On-chip Microwave Interconnects, In Institute of Electrical, Information and Communication Engineers Transaction on Electronics, , Vol. E95-c, No. 10, 2012. (ISI-18122)+.

[13] Arash Farkish and Ali Jahanian, Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation, In Institute of Electrical, Information and Communication Engineers Electronic Express Journal, Vol. 8, No. 24, 2012. (ISI-18110)+.

[12] Mohammad Hossein Moaiyeri, Ali Jahanian, and K. Navi, Comparative Performance Evaluation of Large FPGAs with CNFET- and CMOS-based Switches in Nanoscale, In Nano-micro letters, ISSN: 2150-5551, Vol.3, No.3, 2011. (ISI-16476)+.

[11] Ali Jahanian, Morteza Saheb Zamani and Hamid Safizadeh, Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology, In Elsevier Integration the VLSI Journal, Vol.44, No.2, 2011. (ISI-12993)+.

[10] Ali Jahanian and Morteza Saheb Zamani, Using the chip master planning in automatic ASIC design flow to improve performance and buffer resource management, In Qazvin Islamic Azad University Journal of Computer and Robotics (QJCR), 2011, (SR-23820)+.

[9] Ali Jahanian and Morteza Saheb Zamani, Early buffer planning with congestion control using buffer requirement map, In World Scientific Journal of Circuits, Systems, and Computers (JCSC), Vol. 19, No. 5, pp. 949 973, 2010. (ISI-11105)

[8] Ali Jahanian, Morteza Saheb Zamani, Higher routability and reduced crosstalk noise by asynchronous multiplexing of on-chip interconnects, Transactions on Computer Science and Engineering, In Scientia Iranica International Journal of Science and Technology, Vol. 17, No. 1, pp. 11-24, 2010. (ISI-11086)+.

[7] Mercedeh Sanjabi, Somayeh Maabi, Ali Jahanian, and Sirvan Khalighi, A landmark-based navigation system for high speed cars in the roads with branches, In International Journal of Information Acquisition (IJIA), World Scientific Publishing, Vol.6, No.3, pp. 193-209, 2009, (SR-11104)+.

[6] Ali Jahanian, Morteza Saheb Zamani, and E. Khorram, An Improved Standard Cell Placement Methodology using Hybrid Analytic and Heuristic Techniques, In Qazvin Islamic Azad University Journal of Computer and Robotics (QJCR), Vol.1, No.5, 2008, (SR-11599).

[5] Ali Jahanian and Morteza Saheb Zamani, M. Rezvani, and M. Najibi, Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability, In Springer’s Communications in Computer and Information Science, Advances in Computer Science and Engineering, Germany, pp. 689-696, 2008, (SR-11087)+.

[4] Ali Jahanian and Morteza Saheb Zamani, Using metro-on-chip in physical design flow for congestion and routability improvement, Microelectronics Journal of Elsevier, Vol.39, No. 2, pp.261-274, 2008. (ISI-11082)+

[3] Ali Jahanian and Morteza Saheb Zamani, Buffer distribution in floorplanning stage to decrease the buffer number and congestion control, In The CSI Journal on Computer Science and Engineering, Vol. 5, No. 3, pp. 12-22, 2007, (SR-11085).

[2] Mehdi Saeedi, Morteza Saheb Zamani and Ali Jahanian, Evaluation, prediction and reduction of routing congestion, In Microelectronics Journal of Elsevier, Vol. 38, No. 8, pp. 942-958, 2007. (ISI-11083)+

[1] Ali Jahanian and Morteza Saheb Zamani, Metro-on-Chip: an efficient physical design technique for congestion reduction, In Institute of Electrical, Information and Communication Engineers Electronic Express Journal, Vol.4, No.16, pp.510–516,  2007. (ISI-11084)+