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Ramin Rajaei Assistant Professor Shahid Beheshti University Department of Electrical Engineering |
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Keywords: Ramin Rajaei Ramin Rajaee ÑÇãیä ÑÌÇÆی ÑÇãیä ÑÌÇیی |
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Keywords: Ramin Rajaei Ramin Rajaee ÑÇãیä ÑÌÇÆی ÑÇãیä ÑÌÇیی ϘÊÑ ÑÇãیä ÑÌÇÆی ÔåیÏ ÈåÔÊی Dr Ramin Rajaei Dr Ramin Rajaee Prof Ramin Rajaei ϘÊÑ ÑÇãیä ÑÌÇیی |
Selected Publications (2011-now)
Amirany, R. Rajaei, Fully Nonvolatile and Low Power Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction with Spin-Hall Effect Assistance, IEEE Transactions on Magnetics (TMAG), 2018. R. Rajaei, A. Gholipour, Low Power, Reliable, and Nonvolatile MSRAM Cell for Facilitating Power Gating and Nonvolatile Dynamically Reconfiguration, IEEE Transactions on Nanotechnology (TNANO), 2018. R. Rajaei, A Reliable, Low Power, and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics, Journal of Circuits, Systems and Computers (JCSC), World Scientific, 2018. R. Rajaei, A. Amirany, Reliable, High-Performance, and Nonvolatile Hybrid SRAM/MRAM-based Structures for Reconfigurable Nanoscale Logic Devices, Journal of Nanoelectronics and Optoelectronics (JNO), 2018. R. Rajaei, Design of a Low-Power, High-Performance, and Soft-Error Immune Flip-flop for Nanometer Technologies, Tabriz Journal of Electrical Engineering (TJEE) 2018. A. Amirany, R. Rajaei, Low Power, and Highly Reliable Single Event Upset Immune Latch for Nanoscale CMOS Technologies, The 26th Iranian Conference on Electrical Engineering (ICEE), 2018. A. Gholipour, R. Rajaei, Magnetization Vector Control and Resistance Analysis of STT p-MTJ Devices, The 26th Iranian Conference on Electrical Engineering (ICEE), 2018.
R. Rajaei, Highly Reliable and Low-Power Magnetic Full-Adder Designs for Nanoscale Technologies, Microelectronics Reliability (MR), Elsevier, 2017. R. Rajaei, S. Bakhtavari, A Nonvolatile, Low-Power, and Highly Reliable MRAM Block for Advanced Microarchitectures , IEEE Transactions on Device and Materials Reliability (TDMR), 2017. R. Rajaei, S. Bakhtavari, Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design, IEEE Transactions on Device and Materials Reliability (TDMR), 2017. R. Rajaei, Single Event Double Node Upset Tolerance in MOS/Spintronic Sequential and Combinational Logic Circuits, Microelectronics Reliability (MR), Elsevier, 2017. N. Rajaei, R. Rajaei, M. Tabandeh, “A Soft Error Tolerant Register File for Highly Reliable Microprocessor Design,” International Journal of High Performance Systems Architecture, 2017.
R. Rajaei, Radiation Hardened Design of Nonvolatile MRAM-based FPGA, IEEE Transactions on Magnetics (TMAG), 2016. R. Rajaei, B. Asgari, M. Tabandeh, M. Fazeli, Single Event Multiple Upset-Tolerant SRAM Cell Designs for Nano-scale CMOS Technology, Turkish Journal of Electrical Engineering & Computer Sciences, 2016. R. Rajaei, Design of a Radiation Hardened Register File for Highly Reliable Microprocessors, International Journal of Engineering and Manufacturing (IJEM), 2016. N. Rajaei, R. Rajaei, A Novel Radiation Hardened Parallel IO Port for Highly Reliable Digital IC Design, International Journal of Modern Education and Computer Science, 2016. R. Rajaei, S. Bakhtavari, F. Eslaminasab, Radiation Hardening by Design for Nonvolatile Magnetic Flip-Flops, The 1st International Conference on New Research Achievements in Electrical and Computer Engineering, Tehran, Iran, 2016 (Best Paper Award). R. Rajaei, S. Bakhtavari, A New Fast and Accurate Method for Soft Error Propagation Probability Estimation in Combinational Logic, (in Persian), The 1st International Conference on New Research Achievements in Electrical and Computer Engineering, Tehran, Iran, 2016. S. Bakhtavari, R. Rajaei, Comparison of Carbon Nanotubes and Boron Nitride Nanotubes Properties and their Applications in Nanoelectronics, (in Persian), The 3rd National Conference on New Iranian Technologies in Chemistry, Petrochemical and Nano, Tehran, Iran, 2016.
R. Rajaei, M. Tabandeh, M. Fazeli, Low Cost Circuit-Level Soft Error Mitigation Techniques for Combinational Logic, Transactions on Electrical and Computer Engineering, Scientia Iranica, Elsevier, 2015. R. Rajaei, B. Asgari, M. Tabandeh, M. Fazeli, Design of Robust SRAM Cells Against Single Event Multiple Effects for Nanometer Technologies, IEEE Transactions on Device and Materials Reliability (TDMR) 2015.
R. Rajaei, M. Fazeli, M. Tabandeh, Soft Error-Tolerant Design of MRAM-based Non-Volatile Latches for Sequential Logics, IEEE Transactions on Magnetics (TMAG), 2014. R. Rajaei, M. Tabandeh, M. Fazeli, Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations, Journal of Circuits, Systems and Computers (JCSC), World Scientific, 2014. R. Rajaei, M. Tabandeh, M. Fazeli, Soft Error Rate Estimation for Combinational Logic in Presence of Single Event Multiple Transients, Journal of Circuits, Systems and Computers (JCSC), World Scientific, 2014.
R. Rajaei, M. Tabandeh, M. Fazeli, Low Cost Soft Error Hardened Latch Designs for Nano-scale CMOS Technology in presence of Process Variation, Microelectronics Reliability (MR), Elsevier, 2013.
R. Rajaei, M. Tabandeh, B. Rashidian, Single Event Upset Immune Latch Circuit Design Using C-Element, The IEEE 9th International Conference on ASIC (ASICON2011), 25-28 Oct, 2011, Xiamen, China. R. Rajaei, S. Hessbi, B. Vosoughi Vahdat, An Energy-Aware Methodology for Mapping and Scheduling of Concurrent Applications in MPSoCs, The 19th Iranian conference on electrical engineering (ICEE 2011), Tehran, Iran, May 17-19, 2011.
Þ my previous homepage on SUT server…>>> |
