Course Description
This course introduces the architecture and organization of the conventional and modern micro-processors and micro-controllers. It covers the organization of CISC and RISC processors, the concept of instruction set architecture, performance evaluation of computer systems, computer arithmetic, memory hierarchy, I/O mechanisms and a review on modern multi-core processors. Contents of the course will be examined with hardware implementation of the processors.
Course References
- Morris Mano, Computer System Architecture, 1993.
- David A. Patterson and John L. Hennessy, Computer Organization and Design, The Hardware / Software Interface, MIPS Edition, 2017.
Course Outline
|
Session |
Subject |
Reference |
| 1 | Computer Abstractions and Technology | Chapter 1 from [1] |
| 2 | Register Transfer and Micro-operations | Chapter 4 from [2] |
| 3 | Basic Computer Design | Chapter 5 of [2] |
| 4 | Basic Computer Design | Chapter 5 of [2] |
| 5 | Basic Computer Design | Chapter 5 of [2] |
| 6 | Basic Computer Design | Chapter 5 of [2] |
| 7 | Basic Computer Design | Chapter 5 of [2] |
| 8 | Programming the Basic Computer | Chapter 6 of [2] |
| 9 | Programming the Basic Computer | Chapter 6 of [2] |
| 10 | Micro-programming | Chapter 7 of [2] |
| 11 | Design Review 1 (CISC Design) | Chapter 4 from [1] |
| 12 | Performance Evaluation | Chapter 4 from [1] |
| 13 | RISC and Pipelined Computers | Chapter 4 from [1] |
| 14 | RISC and Pipelined Computers | Chapter 4 from [1] |
| 15 | RISC and Pipelined Computers | Chapter 4 from [1] |
| 16 | RISC and Pipelined Computers | Chapter 4 from [1] |
| 17 | RISC and Pipelined Computers | Chapter 4 from [1] |
| 18 | Design Review 2 (Pipeline Computer Design) | |
| 19 | Computer Arithmetic | Chapter 3 From [1] |
| 20 | Computer Arithmetic | Chapter 3 From [1] |
| 21 | Computer Arithmetic | Chapter 3 From [1] |
| 22 | Computer Arithmetic | Chapter 3 From [1] |
| 23 | Memory Hierarchy | Chapter 12 from [2] |
| 24 | Memory Hierarchy | Chapter 12 from [2] |
| 25 | Memory Hierarchy | Chapter 12 from [2] |
| 26 | Memory Hierarchy | Chapter 12 from [2] |
| 27 | Design Review 3 (Cache Design) | |
| 28 | Input/output | Chapter 11 from [2] |
| 29 | Input/output | Chapter 11 from [2] |
| 30 | Multiprocessor Architectures (NoCs) | Chapter 6 from [1] |
| 31 | Multiprocessor Architectures (Multicores) | Chapter 6 from [1] |
| 32 | Multiprocessor Architectures (Multicores) | Chapter 6 from [1] |
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