Course Description
The course will cover the techniques and algorithms for physical design of Integrated circuits. Topics include partitioning, floor-planning, placement, and routing of electronic chips. Bulk of new challenges in modern chip design corresponding with proposed techniques to fix them will be discussed in the class. This course make a good view on low level chip design and manufacturing for graduate (and post-graduate) students and may open a wide research aspect for them.
Course References
- Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure, 2022.
- N. Sherwani, “Algorithms For VLSI Physical Design Automation”, Kluwer Academic Publishers, 3rd edition, 2002.
- Research papers (Will be introduced during the course)
Grading
- Homework and Projects: 40%
- Research / presentation: 20%
- Final exam: 40%
Outline
Session | Subject | Ref. |
1 | Introduction and motivation | [1] |
2 | Digital design flow and physical design stage | [1] |
3 | A review on layout, 2D and 3D processing and Emerging VLSI technologies | Papers |
4 | Design styles and chip packaging | [1] |
5 | Data structures an basic algorithms: optimization and complexity theory | [1] |
6 | Data structures an basic algorithms: Review on graph theory | [1] |
7 | Data structures an basic algorithms: Introducing the Atlas Development Toolkit (ADT) | [1] |
8 | Partitioning | [1] |
9 | Partitioning | [1] |
10 | Floorplanning | [1] |
11 | Floorplanning | [1] |
12 | New trends for partitioning and Floorplanning (3D architectures, HMetis, …) | Papers |
13 | Placement the cells and IOs | [1] |
14 | Placement the cells and IOs | [1] |
15 | New trends in placement (placement for 3D architectures) | Papers |
16 | New trends in placement (Performance driven) | Papers |
17 | Global routing | [1] |
18 | Global routing | [1] |
19 | New trends in global routing (Box router, Hot-spot management, …) | Papers |
20 | Buffer Insertion and planning | Papers |
21 | Detailed routing | [1] |
23 | Detailed routing | [1] |
24 | New trends in detailed routing | Papers |
25 | Clock routing | Papers |
26 | Physical design of FPGAs | Papers |
27 | Physical design of FPGAs | Papers |
28 | Physical design of FPGAs | Papers |
29 | Process variation and soft errors | Papers |
30 | New interconnect technologies | Papers |
31 | Student seminars | |
32 | Student seminars |
For more details refer to <courseware.sbu.ac.ir>.