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Journal
papers:
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1. |
M.
Moghaddam,
S. Timarchi,
M.H. Moaiyeri,
M. Eshghi, "An
Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques,"
CIRCUITS SYSTEMS AND SIGNAL PROCESSING, ISI,
First
online: 24
July 2015, pp. 1-19. |
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2. |
M.
Fazlali, H. Valikhani, S. Timarchi, H. Tabatabaee, "Fast Architecture
for Decimal Digit Multiplication," Microprocessor and Microsystem, Elsevier,
ISI, Vol. 39, Issues 4–5, June–July 2015, pp. 296–301. |
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3. |
M. Abbasi Alaie, S.
Timarchi, "Efficient modulo 2n +1 multiplier", accepted in Int. J.
Computer Aided Engineering and Technology, 2014. |
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4. |
S. Timarchi, M.
Fazlali,
"Generalized Fault-Tolerant Stored-Unibit-Transfer RNS Multiplier for Moduli
Set {2n-1, 2n, 2n+1}", IET Computers &
Digital Techniques, vol. 6, issue 5, Sep. 2012, pp. 269-276. |
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5. |
M. Saremi, S. Timarchi,
"Efficient Modular Binary Signed-Digit Multiplier for the moduli set {2n-1,
2n, 2n+1}", the CSI Journal of Computer Science and Engineering, Vol. 9, No.
2 & 4(b), pp. 52-62, 2011.
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6. |
A. Sabbagh, K.
Navi, Ch. Dadkhah, O. Kavehei, and S. Timarchi, "Efficient Reverse
Converter Designs for the New 4-Moduli Sets {2n–1, 2n,
2n+1, 22n+1–1} and {2n–1, 2n+1,
22n, 22n+1} Based on New CRTs", IEEE Trans. Circuit
and Systems I, vol.57, no.4, April 2010. |
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7. |
S. Timarchi,
K. Navi, "Arithmetic Circuits of Redundant SUT-RNS", IEEE Trans.
Instrumentation and Measurement, vol.58, no.9, Sep. 2009, pp.2959-2968. |
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8. |
K. Navi, M.
Maeen, V. Foroutan, S. Timarchi, and O. Kavehei, "A Novel Low-Power
Full-Adder Cell for Low Voltage ", Integration, the VLSI Journal,
vol. 42, Issue 4,
Sep.
2009, pp. 457-467. |
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9. |
S. Timarchi,
K. Navi, "A New Aalgorithm for Determining All Possible Symmetric Hybrid
Redundant Numbers," IEICE Electronics Express, Vol.6, No.1, pp.8-13, January
10, 2009. |
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10. |
S. Timarchi,
O. Kavehei, K. Navi, "Low Power Modulo 2n+1 Adder Based on Carry
Save Diminished-One Number System," American Journal of Applied Sciences 5
(4), pp.312-319, 2008. |
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11. |
S. Timarchi,
K. Navi, "Improved Modulo 2n+1 Adder Design," International
Journal of Computer and Information Science and Engineering, Vol. 2, No.3,
pp. 158-165, Summer 2008. |
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Conference
papers:
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1. |
N. Akbarzadeh, S. Timarchi,
A.A. Hamidi, "Efficient Multiply-add Unit Specified for DSPs Utilizing
Low-Power Pipeline Modulo 2n+1 Multiplier," 9th Iranian Conference on
Machine Vision and Image Processing, November 18-19, 2015; Shahid Beheshti
University, Tehran, Iran. |
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2. |
احمد
شعبانی، سمیه تیمارچی، "
معماري كم‌مصرف براي تبديل گسسته كسينوسي بر پايه ساختار كورديك پيش بيني جديد،"
نهمين كنفرانس ماشين بينايي و پردازش تصوير ايران،
دانشگاه
شهید
بهشتی،
آبان
ماه
1394 |
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3. |
S. Timarchi,
N. Akbarzadeh, A.A. Hamidi, "Maximally Redundant High-Radix Signed-Digit
Residue Number System", 18th CSI International symposium on Computer
Architecture and Digital Systems (CADS2015) |
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4. |
A. Najafi, S. Timarchi,
A. Najafi, "High-speed energy-efficient 5:2 compressor", 37th International
Convention on information and communication technology, electronics and
microelectronics, 2014, pp. 80-84. |
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5. |
L. Rahimzadeh, M. Eshghi,
S. Timarchi, "Radix-4 Implementation of Redundant Interleaved Modular
Multiplication on FPGA", the 22nd Iranian Conference on Electrical
Engineering (ICEE 2014), pp. 523-526. |
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6. |
مسعود
عباسی علایی، سمیه تیمارچی، "
پياده سازي بهينه
الگوريتم هاي نهان نگاري با قابليت پيكربندي مجدد"، بيست و دومين كنفرانس
مهندسي برق ايرانICEE2014،
صفحات 2563- 2568 |
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7. |
اردوان
یزدی، سمیه تیمارچی، "پردازنده چند هسته اي پايگاه پردازش داده در شبكه
حسگرهاي بي سيم"، بيست و دومين كنفرانس مهندسي برق ايرانICEE2014،
صفحات 3465 - 3470 |
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8. |
S. Timarchi,
M. Saremi,
M. Fazlali, G. Gaydadjiev,
“High-speed
binary signed-digit RNS adder with posibit and negabit encoding,” accepted
in 21st IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC), October 7-9, 2013. |
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9. |
M. Saremi, S.
Timarchi, “Efficient 1-out-of-3 Binary Signed-Digit Multiplier for the
moduli set {2n-1, 2n, 2n+1},” accepted in 17th CSI International symposium
on Computer Architecture and Digital Systems (CADS2013), October 30-31,
2013,
pp. 123-124. |
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10. |
M. Saremi, S.
Timarchi, “1-out-of-3 Binary Signed-Digit Modular Adder,” 5-th
conference on Information & Knowledge Technology (IKT), May 22-24, 2013. |
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11. |
S. Timarchi,
P. Ghayour and A. Shahbahrami “A Novel High-Speed Low-Power Binary
Signed-Digit Adder” accepted in 16th CSI International symposium on Computer
Architecture and Digital Systems (CADS2012),
(Published by IEEE).
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12. |
S. Timarchi,
M. Fazlali and Sorin Dan Cotofana " Reliable Structure for Moduli Set
{2n-1, 2n, 2n+1} Adders Based on a Novel RNS Representation " The 28th
IEEE International Conference on Computer Design (ICCD 2010), Amsterdam, the
Netherlands, 3-6 October, 2010.
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13. |
S. Timarchi
and M. Fazlali " Power-Area-Delay Efficient Modulo 2n-1
Multiplier for Multiply-Accumulate Unit " The 15th CSI International
Symposium on Computer Architecture and Digital Systems (CADS2010), IPM,
Tehran, 23-24 September, 2010, (Published by IEEE).
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14. |
S. Timarchi,
K. Navi, and O. Kavehei, "Maximally Redundant High-Radix Signed-Digit Adder:
New Algorithm and Implementation" IEEE Computer Society Annual Symposium on
VLSI (ISVLSI), May 13-15, 2009, Tampa, Florida. |
|
15. |
S. Timarchi,
K. Navi, "
Efficient Class of Redundant Residue Number
", IEEE International Symposium on Intelligent Signal Processing (WISP), pp.
475-480, 3-5 October 2007, Madrid, Spain. |
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16. |
S. Timarchi,
K. Navi, “A Novel Modulo 2n+1 Adder Scheme”, 12th International
CSI Computer Conference (CSICC’2007), Shahid Beheshti University, 20-22
February 2007, Tehran, Iran |
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17. |
M. Hosseinzade, S. Timarchi, and K. Navi, "Multi Level Residue Number
System with Moduli Set of (2n, 2n-1, 2n-1-1)
", 12th International CSI Computer Conference (CSICC’2007), Shahid Beheshti
University, 20-22 February 2007, Tehran, Iran. [Farsi] |
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18. |
S. Timarchi,
A. Zakeralhosseini, "A Novel Square Root Algorithm Using Multi Expert
Systems", 12th International CSI Computer Conference (CSICC’2007),
Shahid Beheshti University, 20-22 February 2007, Tehran, Iran. [Farsi] |
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19. |
M. Garailoo, S. Timarchi, and K. Navi, and Mahsa Garailoo, "Origami
and Encryption Algorithms", 12th International CSI Computer Conference
(CSICC’2007), Shahid Beheshti University, 20-22 February 2007, Tehran, Iran.
[Farsi] |
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20. |
S. Timarchi,
K. Navi, and M. Hosseinzade, "VLSI Design of RNS Subtracter for modulo(2n+1)",
11th International CSI Computer Conference (CSICC’2006), School of Computer
Science, IPM, Jan. 24-26, 2006, Tehran, Iran. [Farsi] |
|
21. |
M. Hosseinzade, K. Navi, and S. Timarchi, "New VLSI Design of 4-3
Compressor", 11th International CSI Computer Conference
(CSICC’2006), School of Computer Science, IPM, Jan. 24-26, 2006, Tehran,
Iran. [Farsi] |
|
22. |
S. Timarchi,
K. Navi, and M. Hosseinzade, "New Design of RNS Subtracter for modulo (2n+1)",
2nd IEEE International Conference on Information & Communication
Technologies: from Theory to Applications (ICTTA), 24-28 Apr 2006, Damascus,
Syria. |
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23. |
M. Hosseinzade, A. Mirbaha, S. Timarchi, and K. Navi, "Design of
Current Mode Circuits of Residue Number Systems", 11th International
Conference of Electrical Engineering (ICEE’2006), Amirkabir University of
Technology, Tehran, Iran. [Farsi] |
|
24. |
M. Hosseinzade, S. Timarchi, A. Mirbaha, and K. Navi, "Design of
New High Speed Multiple Operand RNS Adder", 11th International
Conference of Electrical Engineering (ICEE’2006), Amirkabir University of
Technology, Tehran, Iran. [Farsi] |
|
25. |
S. Timarchi,
S.G. Miremadi, A.R. Ejlali, "A Comparative Evaluation of Some
Hardware-Based Pseudo-Random Number Generators", 10th International CSI
Computer Conference (CSICC 2005), January 24-26, 2005, Tehran, Iran |
|
26. |
S. Timarchi,
S. G. Miremadi, A.R. Ejlali, "Evaluation of Some Exponential Random
Number Generators", 10th International CSI Computer Conference (CSICC
2005), January 24-26, 2005, Tehran, Iran. [Farsi]. |
|
27. |
S. Timarchi,
S.G. Miremadi, A.R. Ejlali, "Evaluation of Some Exponential Random Number
Generators Implemented by FPGA", IASTED International Conference on
Parallel and Distributed Computing and Networks (PDCN), February 15-17, 2005
Innsbruck, Austria |
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Presentations:
|
|
1.
|
Ph.D. Thesis:
Design and Implementation of Efficient Redundant Residue
Number Systems |
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2.
|
ICCD 2010 Conference: A Unified Addition Structure for Moduli Se {2n-1,
2n,2n+1} Based on a Novel RNS Representation |
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