Publications

[1] M. Zomorodi, M. A. Taherkhani, K. Navi, "Synthesis and Optimization by Quantum Circuit Description Language," In Transactions on Computational Science XXIV, pp. 74-91. Springer Berlin Heidelberg, 2014.

[2] M. Nezakatolhoseini, M. A. Taherkhani, "A Framework For Performance Evaluation of ASIPS In Network-Based IDS," CoRR abs/1211.0620, 2012.

[3] F. Sharifi, S. Amanollahi, M. A. Taherkhani, O. Hashemipour, "A Flexible Design for Optimization of Hardware Architecture in Distributed Arithmetic based FIR filters," RadioElectronics & Informatics, vol. 4, pp. 25-30, 2012.

[4] M. A. Taherkhani, M. Abbaspour, "An Efficient Hardware Architecture for Deep Packet Inspection in Hybrid Intrusion Detection Systems," In 4th Int. Conf. on Communications and Networking in China, August 26-28, 2009.

[5] M. Esmaeil-doust, N. Kazemi-fard, M. A. Tehrani, M. A. Taherkhani, M. Abbaspour, "Power and performance optimized NoC based Systems Design Flow," In Proc. IEEE EWDTS, 2007.

[1] M. A. Taherkhani, M. Abbaspour, "A Layered Hardware Architecture for Anomaly based Intrusion Detection Systems," Tech. Report, Network Lab., Dept. of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran, ECE-NL-TR-09-124, Apr. 2009. (In Persian)

[2] M. A. Taherkhani, M. Abbaspour, "Hardware Architectures for Network based Intrusion Detection Systems, A Survey and Taxonomy", Tech. Report, Network Lab., Dept. of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran, ECE-NL-TR-08-121,.Dec. 2008. (In Persian)