• Z,   Torabi   and   A.   Belghadr,   “Fast   and   Power   Efficient   Signed/Unsigned   RNS   Comparator   &   Sign   Detector,” Journal   of   Electrical   and   Computer   Engineering   Innovations   (JECEI),      doi:   10.22061/jecei.2022.8321.505, 2022. • A.   Belghadr   and   G.Jaberipur,   “Efficient   variable-coefficient   RNS-FIR   filters   with   no   restriction   on   the moduli   set,”   Signal,   Image   and   Video   Processing,   Springer,   https://doi.org/10.1007/s11760-021-02097-9, 2022. • Z.   Torabi,   G.   Jaberipur   and   A.   Belghadr,   “   Fast   division   in   the   residue   number   system   {2^n + 1,   2^n,   2^n- 1}   based   on   shortcut   mixed   radix   conversion,”   Computers   and   Electrical   Engineering,   Volume   83,   May 2020 • Z.   Torabi   and   A.   Belghadr,   “An   RNS   Comparator   via   Dynamic   Range   Partitioning:   The   Case   of   {2^n   -   1, 2^n, 2^(n+1) -1},” The CSI Journal on Computer Science and Engineering, Volume 16, No. 2, 2019. • G.   Jaberipur,   A.   Belghadr   and   S.   Nejati,   “Impact   of   diminished-1   encoding   on   residue   number   systems arithmetic   units   and   converters,”   Computers   and   Electrical   Engineering,   Volume   75,   Pages   61–76,   May 2019. • A.   Belghadr   and   G.   Jaberipur,   “FIR   Filter   Realization   via   Deferred   End-Around   Carry   Modular   Addition,” in   IEEE   Transactions   on   Circuits   and   Systems   I:   Regular   Papers,   Volume   65,   No.   9,   Pages   2878-2888,   Sep. 2018. • G.   Jaberipur   and   A.   Belghadr,   “(5+2logn)ΔG   diminished-1   modulo-(2^n+1)   unified   adder/subtractor   with full zero handling,” Computers and Electrical Engineering, Volume 61, Pages 95–103, July 2017. • A.   Belghadr   and   A.   Jahanian,   “Three-Dimensional   Physical   Design   Flow   for   Monolithic   3D-FPGAs   to Improve   Timing   Closure   and   Chip   Area,”   Journal   of   Circuits,   Systems   and   Computers,   Volume   26,   No.   10, 2017. • H.    Sharifi,    F.    Sharifi,    and    A.    Belghadr,    “Low-Power    CMOS/Nanomaterial    Three-Dimensional    Field Programmable Gate Array Architecture,” Quantum Matter, Volume 5, No. 4, Pages 612-615, 2016. • A.   Belghadr   and   A.   Jahanian,   “Metro-on-FPGA:   A   feasible   solution   to   improve   the   congestion   and   routing resource   management   in   future   FPGAs,”   Integration,   the   VLSI   Journal,   Volume   47,   Issue   1,   Pages   96-104, January 2014. • S.   A.   Edwards,   "MEMOCODE   2012   hardware/software   codesign   contest:   DNA   sequence   aligner,"   Tenth ACM/IEEE   International   Conference   on   Formal   Methods   and   Models   for   Codesign   (MEMCODE2012), Arlington, VA,  pp. 85-90, 2012.