• 2013 – 2019 PhD  in Computer Engineering, Computer Architecture       Shahid Beheshti University, Tehran, Iran Title : Fast and Power Efficient Residue Number Systems via Deferred End-Around Carry Operations       Under supervision of Prof. G. Jaberipur • 2011 – 2013 MSc  in Computer Engineering, Computer Architecture    Shahid Beheshti University, Tehran, Iran    Title: New Architecture and CAD Flow for  Monolithically Stacked 3D FPGAs.   Under supervision of Prof. A. Jahanian      GPA: 19.13/20, Grade A • 2007 – 2011 BSc in Computer Engineering, Hardware Engineering    Shahid Beheshti University, Tehran, Iran    Title: Hardware design and implementation of a pipelined NoC (Network on Chip) on FPGA using VHDL.    Under supervision of Prof. A. Jahanian      GPA: 16.58/20 • 2003 – 2007 High School Allameh Tabatabaei - Complex of Cultural and Educational units (ATCCE), Tehran, Iran    Diploma of Mathematics and Physics Discipline